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Congestion Driven Placement for VLSI Standard Cell Design Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada December. - ppt download
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Planning for local net congestion in global routing | Proceedings of the 2013 ACM International symposium on Physical Design
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A gcell in which a routing blockage occupies 90% of the capacity. If... | Download Scientific Diagram
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Multimedia Gallery - Routing congestion on integrated circuits is one of the physical limits to computation. | NSF - National Science Foundation
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Routing Congestion in VLSI Circuits: Estimation and Optimization (Integrated Circuits and Systems): Saxena, Prashant, Shelar, Rupesh S., Sapatnekar, Sachin: 9781846283536: Amazon.com: Books
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